1. Field of the Invention
The present invention relates to improving manufacturing yield for microprocessor chips by providing redundant registers and accurately identifying those registers which are available for use. More particularly, the present invention includes a sparing technique that tests the register file circuitry and stores the results of these tests in order to ensure that a sufficient number of registers are available to meet the baseline specification of the microprocessor.
2. Description of Related Art
With the continual advance of computer technology, more and more circuitry is being provided on each integrated circuit (IC), which makes them correspondingly more complex. These chips are likely to include millions of transistors and be quite large. It is not surprising that the cost to fabricate these ICs is relatively high and, as the cost increases, the manufacturing yield becomes critical in order for producers of these chips to remain competitive.
Manufacturing yield is essentially the percentage of ICs that meet the design specification relative to the total number of chips produced. Of course, as chip complexity and size increases, the manufacturing yield usually decreases. Further, after a new IC design has been manufactured for a significant period of time, per chip costs often decrease as the fabrication process is tuned and optimized. Thus, in order to stay competitive it is often necessary, if not critical, to increase manufacturing yields especially during the early stages of chip production when the manufacturing costs are highest.
It can be seen that yield on large chips is an important issue and techniques for tolerating small numbers of random defects in the manufacturing process are increasingly more important. While the use of redundancy in caches has been used for some time, it has not been used for other structures in microprocessors. In particular, redundancy has not been used in the microprocessor register file circuitry that is common in microprocessors and whose area contribution is growing due to the expanded use of register renaming. Further, the contribution of the register file and instruction buffer to the overall core area of modern microprocessors is increasing to the point where both of these structures can make up approximately ten percent (10%) of the microprocessor core for a total of about 20% of the core area and core functionality. This illustrates the importance in terms of complexity and size of just two microprocessor core structures where redundancy can be used in accordance with the present invention to improve performance.
In a microprocessor with renamed registers, the machine automatically maps the architecturally defined set of xe2x80x9clogical registersxe2x80x9d into a larger set of xe2x80x9cphysical registersxe2x80x9d to avoid various types of false dependencies and to allow easy purging or speculative results when necessary. As instructions are processed and registers are needed, register allocation/deallocation logic examines the state of the physical register pool, and selects a register that is currently not active, and then marks it as xe2x80x9cin usexe2x80x9d. Later, when the instruction is either completed (or purged), the register deallocation logic frees the register again for future use.
More particularly, most modem microprocessors use rename buffers, or registers. It should be noted that the terms xe2x80x9crename registersxe2x80x9d and xe2x80x9crename buffersxe2x80x9d will be used interchangeably herein. These rename buffers act as temporary storage for instructions that have not completed and as write-back buffers for those that have. To avoid contention for a given register location rename registers are provided for storing instruction results before they are completed and committed to the architected registers. For example, a microprocessor ray include thirty-two, thirty-two bit general purpose registers (GPRs) which are considered architected registers and twelve, thirty-two bit rename registers for holding results prior to their commitment to the architected registers. Further, rename registers may also be provided for other architected registers, such as two rename buffers for the floating point registers (FPR) and eight rename buffers for the condition register (CR).
Generally, when the dispatch unit provides an instruction to the appropriate execution unit (i.e. the integer unit (IU), floating point unit (FPU), load/store unit (L/S), or the like), it allocates a rename register for the results of that instruction. The dispatch unit also provides a tag to the execution unit identifying the result that should be used as the operand. When the proper result is returned to the rename buffer it is provided to the execution unit, which begins execution of the instruction. Instruction results are not transferred from the rename registers to the architected registers until any speculative branch conditions are resolved and the instruction itself is retired without exceptions. If a speculatively executed branch is found to have been incorrectly predicted, the speculatively executed instructions following the branch are flushed and the results of those instructions are flushed from the rename registers.
As an example, conventional microprocessors avoid contention for a given register file location, and in the course of out-of-order execution, by providing rename registers for the storage of instruction results prior to their commitment (in program order) by the completion unit to the architecturally defined registers. Register renaming minimizes architectural resource dependencies, namely the output and anti dependencies, that would otherwise limit opportunities for out-of-order execution.
A GPR rename buffer entry is allocated when an instruction that modifies a GPR is dispatched. This entry is marked as allocated but not valid. When the instruction executes, it writes its results to the entry and sets the valid bit. When the instruction completes, its result is copied from the rename buffer entry to the GPR and the entry is freed for reallocation. For load with update instructions that modify two GPRs, one for load data and another for address, two rename buffer entries are allocated.
An instruction that modifies a GPR is assigned a position in the GPR rename register file. Load with update instructions get two positions since they update two registers. When the GPR rename buffer is full, the dispatch unit stalls when it encounters the first instructions that need an entry. A rename buffer entry becomes available in one cycle after the result is written to the GPR.
Operation of rename buffers that may be associated with other register files such as the floating point register file, condition register file, and the like function in a similar manner.
Redundancy and sparing are methods that are known in the art. These techniques supply additional circuit elements, beyond those required for the baseline specification of the IC, to act as spares in the event that certain ones of the original elements prove to be defective.
The use of redundancy in caches has been common for some time, but due to complexity and cycle time considerations has not been used for other structures in microprocessors. The present invention relates to providing redundancy in register file circuitry which, due in part to register renaming, is becoming a larger portion of the microprocessor core in terms of physical area and importance.
Typically, with cache redundancy, fuses are provided that are associated with each cache line. As the cache is tested, those fuses associated with lines that test bad can be blown, or opened, and the array access decoder circuitry is modified to note the state of these fuses. The decoder circuitry then xe2x80x9cdecodes aroundxe2x80x9d any bad entries by recognizing an address to a bad cache line and substituting a functional cache line, while maintaining a record of this substitution. The problem with this traditional scheme is that a significant amount of complexity is required in the cache array circuitry provide the address substitution and tracking mechanism. This is undesirable not only in the amount of additional logic circuitry that is required to be implemented in the chip, but also in the amount of cycle time that is required. More particularly, each time the processor tries to access the portion of the cache that tested bad, decode logic must identify the request as being to the bad address and provide a substitute address to a spare cache location where the data can be stored. This decoding and address substitution occurs continuously during the operation of the data processing system. Thus, it can be seen that a significant amount of cycle time can be consumed over and over during system operations as access attempts to bad cache locations are continually processed.
In a microprocessor core, the register file circuitry is usually considered a critical path which is very sensitive to cycle time pressure. Thus, the conventional cache redundancy decode scheme cannot be applied to a register file circuitry environment and will not solve the problem addressed by the present invention which provides redundant registers without adding significant complexity or negatively impacting cycle time.
Therefore, it can be seen that a need exists for a mechanism that supports redundant microprocessor registers to allow the baseline specification to be met, even when some of the registers may not be functional, and to allow the control of these registers without adding additional complexity or cycle time pressures to the system.
In contrast to the prior art, the present invention is a mechanism for providing redundancy in the register file of a microprocessor such that registers which test bad during manufacturing can be tolerated and the baseline specification of the microprocessor can be met.
Broadly, the present invention utilizes the renaming capability of a microprocessor to allow additional registers, above those called for in the specification to be provided. The registers are then tested and those found xe2x80x9cbadxe2x80x9d are identified and avoided by the allocation/deallocation logic, which is used to assign registers to the various instructions being executed by the microprocessor.
More particularly, the present invention maintains a list of registers that are available to be allocated to various instructions as they execute. The allocated registers are typically used to store interim data resulting from the execution of the assigned instruction. When the data in the rename register is complete it is then committed to the architecture by rewriting the results to an architected register. The present invention uses this rename capability to prevent a register that was manufactured bad to ever be included in the list of registers that are available for allocation to the processor instructions. In this manner redundant or spare registers, above the baseline specification of the microprocessor, can be provided to account for any faulty registers that are present due to a less than 100% manufacturing yield. By using existing logic to prevent those registers that test bad from ever being used, a register file meeting the microprocessor specification is ensured, without the addition of costly and complex control logic, or requiring sorting of the chips to find those which happen to have been manufactured with register file that comply with the specification.
Therefore, in accordance with the previous summary, objects, features and advantages of the present invention will become apparent to one skilled in the art from the subsequent description and the appended claims taken in conjunction with the accompanying drawings.